1. Technical Field
The present invention relates to a pulse generator, and more particularly, to a latch-based pulse generator, which is used in an active matrix type thin film transistor liquid crystal display (TFT-LCD) driver.
2. Discussion of the Related Art
FIG. 1 is a circuit diagram of a common pulse generator 100. Referring to FIG. 1, the pulse generator 100 includes inverters 120 and 140, a flip-flop 110, and a NAND gate 130. As shown in FIG. 1, the inverters 120 and 140 (i.e., complementary metal oxide semiconductor (CMOS) inverters) include positive channel metal oxide semiconductor (PMOS) and negative channel metal oxide semiconductor (NMOS) transistors. The NAND gate 130 also includes two PMOS and NMOS transistors.
The flip-flop 110 latches data DIN input to an input terminal D and outputs the result of the latching to an output terminal Q in response to a clock signal CLK input to a clock terminal CK and a complementary clock signal CLKB input to a complementary clock terminal CKB. The flip-flop 110 is reset in response to a falling edge of a reset signal RSB input to a reset terminal RB.
FIG. 2 is a circuit diagram of the flip-flip 110 shown in FIG. 1. Referring to FIG. 2, the flip-flop 110 includes PMOS transistors 1101, 1105, 1113, and 1117, NMOS transistors 1103, 1107, 1111, and 1115, two inverters 1119 and 1123, and two NAND gates 1109 and 1121.
Referring to FIGS. 1 and 2, the transistors 1101, 1107, 1111, and 1117, the inverter 120, and the NAND gate 130 toggle in response to the clock signal CLK, and the transistors 1103, 1105, 1113, and 1115 toggle in response to the complementary clock signal CLKB.
FIG. 3 is a circuit diagram of a pulse generator 300 that sequentially latches n data. The pulse generator 300 includes first through nth pulse generators 100_1, 100_2 . . . 100_n. The structure of each of the first through nth pulse generators 100_1, 100_2 . . . 100_n is the same or similar to that of the pulse generator 100 of FIG. 1.
The pulse generator 100_1 receives and latches an input signal DIN in response to a clock signal CLK and outputs two output signals DOUBT and L_CLK1. The output signal DOUBT is input to an input terminal DIN2 of a second pulse generator 100_2 and the other output signal L_CLK1 is used as a pulse for latching data.
The second pulse generator 100_2 receives and latches the output signal DOUBT in response to an inverted clock signal CLKB and outputs two output signals DOUT2 and L_CLK2. The output signal DOUT2 is input to an input terminal of a third pulse generator, and the output signal L_CLK2 is used as a pulse for latching data.
In the pulse generator 300, the first through nth pulse generators 100_1, 100_2 . . . 100 _n, are connected in series and generate pulses L_CLK1, L_CLK2 . . . L_CLKn, respectively, in response to clock signals CLK and CLKB. Thus, the pulses L_CLK1, L_CLK2 . . . L_CLKn, which are used to latch related data, are sequentially generated.
For instance, when latching 128 bits of data, a minimum of 128 input clock signals CLK or CLKB are required. In doing so, each of the pulse generators 100_1, 100_2 . . . 100_n, which include the transistors 1101, 1103, 1105, 1107, 1111, 1113, 1115, and 1117, toggle the clock signals CLK and CLKB. Therefore, the output of one pulse generator (e.g., the pulse generator 100_n) toggles a minimum of 127 times to generate a pulse L_CLKn, resulting in excess power consumption.